1. Field of the Invention
Methods and apparatuses consistent with the present invention relate to a memory device, and more particularly, to programming a non-volatile data storage device, in which a fast write operation is enabled when a write operation is performed using interleaving for each channel in a multi-channel system using a plurality of non-volatile data storage devices.
2. Description of the Related Art
Multimedia devices including mobile devices store and provide large-size multimedia data such as MPEG-I Audio Layer 3 (MP3) audio and moving pictures. Since storage devices used in the multimedia devices provide a large storage space, a function of fast reading and writing data should also be provided.
Among non-volatile data storage devices, flash memory is used as a storage device for various mobile devices due to its low power consumption, small size, low generation of heat, and high stability. The size of a storage space in a memory also increases quickly.
FIG. 1 is a block diagram illustrating the internal structure of a flash memory 100 according to the related art. Referring to FIG. 1, the flash memory 100 includes a memory cell array 110 and a page register (page buffer) 120.
The flash memory 100 is a non-volatile memory device in which data can be electrically erased/written repeatedly and is classified into a NOR type and a NAND type according to the connection state between cells and bit lines. The flash memory 100 includes the memory cell array 110 as a storage region for storing information. The memory cell array 110 consists of a plurality of blocks, each of which consists of a plurality of cell strings (also referred to as NAND strings). The page register (page buffer) 120 is provided in the flash memory 100 in order to store data in the memory cell array 110 or to read data from the memory cell array 110. As is well known to those of ordinary skill in the art, the memory cell array 110 of the flash memory 100 is erased or programmed using Fowler-Nordheim (F-N) tunneling current.
For a write operation with respect to the flash memory 100, a write command is given to the flash memory 100 by a controller in order to store data in the memory cell array 110 and an address and data are consecutively input to the flash memory 100. In general, data, which is assigned to be programmed, is sequentially transmitted to the page buffer 120 in units of a byte or word. After the data, which is assigned to be programmed, i.e., data corresponding to one page, is loaded in the page buffer 120. As a result, the data stored in the page buffer 120 is programmed in the memory cell array 110 according to a programming command. Before data is re-written to an already-recorded region, an erase command should be executed first for each block including a plurality of pages. In other words, after an erase operation is performed for each block, which is the basic unit of the erase operation, data is sequentially written in a plurality of pages forming a block. At this time, the written operation with respect to the flash memory 100 includes two steps, i.e., i) moving data that is to be recorded to the page buffer 120 and ii) programming data of the page buffer 120 to the memory cell array 110.
FIG. 2 illustrates a hardware architecture of an N-channel/four-way type using flash memories according to the related art.
In general, a flash memory having a low programming speed and various architectures for preventing a controller from staying in a wait state during programming has been suggested. In FIG. 2, a flash memory controller 210 and four flash memories 221 through 224 for each channel are illustrated. In the case of a first channel 220, when the flash memory is programmed, the four flash memories 221 through 224 are connected by a system bus and interleaving is adopted so as to minimize the wait time of the controller 210.
FIG. 3A is a timing diagram for a write operation with respect to four flash memories in a channel illustrated in FIG. 2, and FIG. 3B illustrates in detail a write operation of a page illustrated in FIG. 3A.
As illustrated in FIG. 3B, in a write operation 310 of a page, when a page unit of 2 KB is applied, setup time is 51.2 μsec (setup time for 1 Byte is 25 nsec) and programming time is 200 μsec. To compensate for slow programming time, large-size data is distributed over four flash memories of each channel for storage, as illustrated in FIG. 2. According to the related art, when programming is performed in a flash memory, setup is performed in another flash memory in an idle state within the same channel so as to minimize the wait time of the controller, thereby implementing a faster write operation.
However, according to the related art, since a non-volatile data storage device like a flash memory uses a single page buffer, it requires a setup time between consecutive program operations. The setup time interrupts the consecutive program operations and reduces the maximum recording speed of a single flash memory. Moreover, when a plurality of flash memories is used as in FIG. 2, if all the flash memories are programmed, the controller 210 cannot perform a setup operation and enters a wait state. In other words, if the operating time of a flash memory according to common performance includes an erasure time of 1500 μsec, a page programming time of 200 μsec, and a one-page setup time of 51.2 μsec (25 nsec for 1 Byte setup), a wait time of 46.4 μsec is generated after four setup operations, in theory, in a 4-way architecture. If the controller 210 could continue performing the setup operation during the wait time, the performance of the entire system would be improved.